SW/FW Automated Test Framework and Debug Toolkit for System Testing In Design/IP Track Presentation of the 53rd Design Automation Conference (DAC 2016, Austin TX, Jun 4 – Jun 9, 2016)
This presentation outlines a novel SW/FW automated test framework and debug toolkit for system testing that supports automated regression and effective interactive debug. The framework is based on Google Test with expansions incorporating C++14 features and various open source libraries. Major features include: test flow utilities, argument parser, JSON files for device configuration, control test equipment via Tcl_Eval(), interactive debug prompt, control of FW running in the embedded CPU via remote gdb, C++ reflective API, etc. Engineers are more productive developing testcase in this test framework develop testcases compare to writing testcase with plain old C in ad-hoc fashion.
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A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration In Proceeding of the DVCON 2015(San Jose, US, Mar 1 – Mar 4, 2015).
PMC’s verification teams started exploring simulation acceleration (SA) with hardware-assisted verification in 2011, as one of the early adopters of UVM Acceleration. They undertook this effort because of the complexity and size of their mixed-language designs, which were coded in SystemVerilog, Verilog, and VHDL, and stimulated using state-of-the-art testbenches coded in UVM-e.
A few years later, the task of porting a design and testbench from simulation to acceleration evolved into a methodology and is now re-used across multiple verification teams. Finally, PMC has achieved the holy grail of SA, conquering the most complex challenges of SA verification including: 1) Speed – achieving 67x speed up, 2) Time to First Test – taking only a month to port a verification environment to run in acceleration mode, 3) Consistent – Running the same tests with RTL and an accelerated DUT, producing the same results.
This methodology exploits essential capabilities of the tools in use, and production proven procedures. This paper outlines a step-by-step guide to port an existing UVM-e testbench to SA. The verification user community can use this paper as a template to plan their migration from simulation to hardware acceleration.
Full Text: pdf (334kb)
Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e In Proceeding of the DVCON 2013(San Jose, US, Feb 24 – Feb 28, 2013).
Given the size and complexity of modern ASICs/SoC, coupled with their tight project schedule, it is impractical to build a complete system or chip level verification environment from scratch. Instead, in order to increase productivity, maximizing reuse of existing verification components seamlessly with the project has become one of the biggest opportunities to increase verification efficiency. In this paper, we present a testbench framework to maximize vertical reuse within a project. The framework presented here has been proven on the ground-up development of a 200M gates ASIC. In our framework, the system testbench is built in a hierarchical manner by recursively importing lower level block or module testbenches. From the lowest level to the highest level, all the testbenches are designed to support plug-and-play integration. Verification engineers can hook up several lower level testbenches and turn them into a higher level testbench. The system testbench inherits the device configuration sequences, traffic generation sequences, checkers and monitors from the imported module testbenches without duplication of effort. As a result, vertical reuse shortens the development time of the system testbench, improves the quality of testbench code and allows fast bring up during system integration.
Full Text: pdf (251kb)
Can You Even Debug a 200M+ Gate Design? In Proceeding of the DVCON 2013(San Jose, US, Feb 24 – Feb 28, 2013).
Verification debug consumes a large portion of the overall project schedule, and performing efficient debug is a key concern in ensuring projects tape out on time and with high quality. In this paper, we outline a number of key verification debug challenges we were faced with and how we addressed them using a combination of tools, technology and methodology. The root cause of failures can be traced, most often, to either an issue in the RTL, an issue in the testbench or, in our case, the software interacting with the hardware. Speeding the debug turnaround time (the time to re-run a failing sim to replicate the issue for debug) is critical for efficient debug. Periodic saving of the simulation state was utilized extensively to narrow the debug turnaround time to a very small window. Once a re-run was launched, waveform verbosity levels could be set by users to dump the appropriate amounts of information for debug of the re-run scenario. For additional performance on the testbench side, coding methodology was introduced that allowed for maximum performance of stable sections of code. To speed SW debug, a software driver was implemented into the testbench to allow for debug of SW related issues very early on in the project.
Full Text: pdf (331kb)
Hardware/Software co-verification using Specman and SystemC with TLM ports In Proceeding of the DVCON 2012(San Jose, US, Feb 28 – Mar 1, 2012).
In modern ASIC/SoC design, the hardware and software have to work seamlessly together to deliver the functions, requirements and performance of the embedded system. To accelerate time-to-market and to reduce overall development cost, it is crucial to co-verify the software code with the hardware design prior to tape-out. The software team can start developing and debugging their code with the actual hardware RTL code to shorten their overall development cycle. The hardware team can use the software code to identify performance bottlenecks and incorrect functional behaviors early in the development cycle which helps to reduce the risk of increasingly expensive device revisions.
The current approach to co-verification is primarily running the software on the embedded processor inside the hardware design, either within the simulator or with ICE (in-circuit emulation). The disadvantage of this approach is slow debug turnaround time and the higher cost is procuring and supporting a dedicated emulation box or FPGA platform. In addition, the software is running in isolation relative to the testbench, hence it is often challenging and inconvenient to integrate the software with other verification IP in the testbench.
In this paper, we will present an alternate approach on how to integrate the software driver into the simulator using Specman and SystemC with TLM ports. The software is running in the same memory space as the testbench, both of which run through the simulator on the Linux host. The advantage of this approach is fast execution speed of the software and the interoperability of the software with other verification components in the testbench. The software code runs in zero simulation time and the testbench has full control of the software using TLM ports and direct memory access via pointers. In addition, the software code can invoke gdb or any other C debugger to make debugging easier.
Full Text: pdf (313kb)
Functional Verifi cation of Next-Generation ICs with Next-Generation Tools: Applying Palladium XP Simulation Acceleration to an Existing Specman Testbench Framework In CDNLive! 2012 (San Jose, US, Mar 13 – Mar 14, 2012).
Next-generation ICs from PMC are ever-larger, to the scale of more than 100M gates. Using conventional simulators, typical datapath simulations for telecom applications can take hours to send a complete frame, while full regression suites can take a week. With more features causing longer simulation times, it’s challenging to complete a comprehensive verifi cation plan while meeting time-to-market demands. To solve this, PMC implemented a transaction-level testbench infrastructure using the Specman Elite® tool, based on the Cadence hardware-acceleration–friendly Universal Verifi cation Methodology (UVM). High-level protocol UVM verifi cation components (UVCs) generate transactions driven to low-level interface UVCs, which generate signals that enter the device under test. To support the Palladium XP hardware acceleration platform, the aspect-oriented programming nature of Specman was exploited. Interface UVCs were extended by splitting BFMs and collectors across Specman and SystemVerilog RTL, leaving protocol UVCs unchanged. Thus, PMC’s verifi cation capabilities expanded with virtually no disruption to its ongoing verifi – cation plan. The addition of Palladium XP provides accelerated simulations that complete in 40x the speed of normal simulations. Thus, regressions can be completed in days instead of weeks and interactive debugging of top-level simulations are now possible, allowing PMC to complete a full verifi cation plan on complex ICs while reducing time to market.
Full Text: pdf (576kb)