{"id":3010,"date":"2009-05-29T01:02:47","date_gmt":"2009-05-29T09:02:47","guid":{"rendered":"http:\/\/www.horace.org\/blog\/?p=3010"},"modified":"2009-05-29T01:02:47","modified_gmt":"2009-05-29T09:02:47","slug":"10-myths-about-verification","status":"publish","type":"post","link":"https:\/\/www.horace.org\/blog\/2009\/05\/29\/10-myths-about-verification\/","title":{"rendered":"10 Myths About Verification"},"content":{"rendered":"<blockquote><p>Every verification engineer should remember this list by heart so that they can educate their managers.  The list is so true that I print a copy and pin it to my cube<\/p><\/blockquote>\n<p><!--more--><br \/>\n<strong><br \/>\n\u201cThis is legacy code no need to verify it\u201d <\/strong>&#8211; Hold your horses! are you 100% sure that you\u2019re dealing with silicon proven code? are you sure that nobody\u2019s touched it since it last worked?<\/p>\n<p><strong>\u201cI can come up with a patch in 5 minutes\u201d<\/strong> &#8211; That\u2019s OK as long as you make sure you don\u2019t end up with a verification environment that looks like a bunch of patches hooked together. Ask yourself how easily it would be to modify or fix your environment a week from today? Isn\u2019t it worth it to take a couple of more minutes and write a robust code?<br \/>\n<strong><br \/>\n\u201cStart checking and plan as you go\u201d<\/strong> &#8211; A big no no! Don\u2019t be tempted into this. Even if your task looks like a piece of cake, always plan in advance. You\u2019ll be amazed to see how many problems can be completely avoided\u2026 With that being said &#8211; I know that some engineers out there prefer to get started and only then stop and plan ahead.<\/p>\n<p><strong>\u201cThis is really simple, no need for a test plan\u201d<\/strong> &#8211; Consider your test plan document as your working contract. Whatever you put in it defines the requirements for your current work. If it\u2019s a simple task then just write a test plan on half a page.<\/p>\n<p><strong>\u201cVerification is not the product, no need to keep software standards\u201d<\/strong> &#8211; True, verification is not the product but still &#8211; when you\u2019re dealing with thousands lines of code, you\u2019d better make sure there is a certain level of consistency, let alone programming errors.<br \/>\n<strong><br \/>\n\u201cDon\u2019t have time to add comments\u201d<\/strong> &#8211; Remember the last time you spent half a day on reverse engineering somebody else\u2019s code? How about your own code?<br \/>\n<strong><br \/>\n\u201cOh I know! Let\u2019s just force the signal from outside\u201d<\/strong> &#8211; Forced wires have this tendency to get forgotten along the way and then reappear at a later stage, usually a week before tapeout\u2026 So be extra careful.<\/p>\n<p><strong>\u201cMust have regression running in the background all the time\u201d <\/strong>&#8211; Regression runs alone can\u2019t do the job. You must have a \u201cRegression Sitter\u201d to monitor and analyze the results or else &#8211; you\u2019re just wearing out your servers.<\/p>\n<p><strong>\u201cWe have reached 100% coverage there\u2019s no point in running more tests\u201d<\/strong> &#8211; Not really. Your coverage model can only capture what you thought about in advance . Obviously a random test bench is capable of generating additional scenarios that might reveal a bug, so don\u2019t stop at 100%. Instead &#8211; enhance the functional coverage model.<\/p>\n<p><strong>\u201cVerifiers should be looking for bugs\u201d<\/strong> &#8211; This is a common misconception of what verification is all about. Verifiers should be focused on building a well constructed, robust and complete test bench. Bugs will come out on their own.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Every verification engineer should remember this list by heart so that they can educate their managers. The list is so true that I print a copy and pin it to my cube<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"lc_iscn_info":[],"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[439],"tags":[453],"class_list":["post-3010","post","type-post","status-publish","format-standard","hentry","category-_knowhow","tag-verification"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>10 Myths About Verification - \u54f2\u5b50\u6232 Philosophist\u2019s Camp<\/title>\n<meta name=\"description\" content=\"Every verification engineer should remember this list by heart so that they can educate their managers. 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I could not agree with this article any more, especially on the last point. We verifiers should education the importance of verification to the company, especially to the executives who make the budget decision. Your tool provider won\u2019t tell you\u2026","rel":"","context":"In &quot;News Clips&quot;","block_context":{"text":"News Clips","link":"https:\/\/www.horace.org\/blog\/category\/_reference\/_newsclips\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":4169,"url":"https:\/\/www.horace.org\/blog\/2010\/03\/11\/challenging-misconceptions-about-verification-languages\/","url_meta":{"origin":3010,"position":1},"title":"Challenging Misconceptions About Verification Languages","author":"hevangel","date":"March 11, 2010","format":false,"excerpt":"Looks like Cadence is finally on offensive and pushing Specman strongly over SystemVerilog. As a long time user of Specman, I would like to see Specman wins the HVL war at the end which will make my skill and experience more valuable. By Richard Goering on March 10, 2010 One\u2026","rel":"","context":"In &quot;News Clips&quot;","block_context":{"text":"News Clips","link":"https:\/\/www.horace.org\/blog\/category\/_reference\/_newsclips\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":4515,"url":"https:\/\/www.horace.org\/blog\/2010\/06\/16\/dac-technical-review-day-2\/","url_meta":{"origin":3010,"position":2},"title":"DAC Technical Review (Day 2)","author":"hevangel","date":"June 16, 2010","format":false,"excerpt":"In the 2nd day of DAC, I attended a technology Session Bridging pre-silicon verification and post-silicon validation, a user track presentation on An Open Database for the Open Verification Methodology Synopsys VCS demo and verification luncheon, visited the booth of the following companies: Realintent, Adlec, IBM, Nextop, eVe, ExpertIO Bridging\u2026","rel":"","context":"In &quot;Daily Scribble&quot;","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":532,"url":"https:\/\/www.horace.org\/blog\/2006\/10\/13\/psl-assertions\/","url_meta":{"origin":3010,"position":3},"title":"PSL assertions","author":"hevangel","date":"October 13, 2006","format":false,"excerpt":"This week I have been spending some time learning PSL assertion at work.? Assertion is a new verification methodology pushing very hard from the EDA venders.? It is a complement to the traditional verification flow, which you have no visibility inside the device.? Assertion allows you put extra checks right\u2026","rel":"","context":"In &quot;Daily Scribble&quot;","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":149,"url":"https:\/\/www.horace.org\/blog\/2005\/07\/11\/myth-of-reuse\/","url_meta":{"origin":3010,"position":4},"title":"Myth of reuse","author":"hevangel","date":"July 11, 2005","format":false,"excerpt":"In the quarterly design analysis meeting, the manager of a cancelled project blamed the failure partly on the delay in verification. In that project, the verification schedule is underestimate at least by a factor of four. I think his comment is not totally fair to the verification team. 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