{"id":4515,"date":"2010-06-16T08:16:52","date_gmt":"2010-06-16T16:16:52","guid":{"rendered":"http:\/\/www.horace.org\/blog\/?p=4515"},"modified":"2010-06-16T08:16:52","modified_gmt":"2010-06-16T16:16:52","slug":"dac-technical-review-day-2","status":"publish","type":"post","link":"https:\/\/www.horace.org\/blog\/2010\/06\/16\/dac-technical-review-day-2\/","title":{"rendered":"DAC Technical Review (Day 2)"},"content":{"rendered":"

In the 2nd day of DAC, I attended a technology Session Bridging pre-silicon verification and post-silicon validation<\/em>, a user track presentation on An Open Database for the Open Verification Methodology<\/em> Synopsys VCS demo and verification luncheon<\/em>, visited the booth of the following companies: Realintent, Adlec, IBM, Nextop, eVe, ExpertIO
\n<\/em><\/p>\n

Bridging pre-silicon verification and post-silicon validation<\/strong><\/p>\n

This technology session has panel discussion on closing the gap between verification and validation. Verification and validation has two very different culture arise from limitation in our work. The industry has the same problem we are facing in PMC. There is problem between control vs speed cost vs effort in testing. Since the test environment is incompatible between the two side, it is a challenge duplicate a problem from one side to the other side. The latest technology is Design for Debug (DFD) to close the loop between validation and verification. The idea of DFD is very simply, insert build in waveform probe and signal poke logic into the silicon, so we have get more control and observability in validation. The DFD is very new, but they are aiming to get the flow standardize and automate just like DFT. Simulator will have hooks to the DFD interface to recreate bugs found in validation or generate vectors and dump it to the device. It is interest to see the statistic of RevA success rate has dropped significantly in the industry, from 29% in 2002 to 28% in 2007, and seeing more Rev on average. DFD can speed up the validation process and better turn around between validation and verification. ClearBlue is a DFD tool and they claim overhead is 1-2% area increase in the silicon. However the Intel panel guests cite a number as high as 10% in their own in-house DFD solution. User can trade off between increasing pin count or adding more probe memory to cope with the bandwidth requirement on the DFD interface.<\/p>\n

An Open Database for the Open Verification Methodology<\/strong><\/p>\n

This presentation come out from a university research project. It’s like what Peter had proposed a few years ago. Hook up a C++ SQL API with Specman and save all the coverage or even packet data to a mySQL database. It is a neat proof of concept exercise, but vManager already took address this question.<\/p>\n

Synopsys VCS demo and verification luncheon<\/strong><\/p>\n

The VCS demo is not really a demo. It’s just marketing slides. However I chatted with the VCS product manager for half an hour after the demo and manage to hear a few interesting things about VCS.<\/p>\n

    \n
  1. Cadence has EP and VM for test planning, Synopsys just use a Excel spreadsheet template.\u00a0 The spreadsheet will suck in the coverage data in XLM format to report the test result.<\/li>\n
  2. VCS multi-core is more advance than I had expected.\u00a0 The user can partition the design along logical blocks (subsystems) and run each block in a different core to speed up the simulation.\u00a0 The Cadence multi-core solution does not partition the design, it merely move some function like waveform dumping, checking assertion, running the testbench in a different core.\u00a0 The catch is each core checks out a SVN license.<\/li>\n
  3. VCS has a new constrain resolver, but they use a different approach than Igen.\u00a0 They don’t break down the generation into ICFS.\u00a0 Looks like there are more than one constraint resolver algorithm out there.\u00a0 They claim the new constrain resolver is better than Cadence, but they are only comparing to pgen.\u00a0 The VCS guy is not aware of igen.<\/li>\n
  4. VCS finally support uni-cov, which supported by Cadence since IES8.2.\u00a0 They have a tool to merge uni-cov files in parallel, kinda like the NHL playoff.\u00a0 I think we can modify our coverage merge script to merge coverage in parallel to avoid crashing.<\/li>\n<\/ol>\n

    Realintent<\/strong><\/p>\n

    This company offer statistic verification tool that runs very early in the development cycle to catch bugs before having testbench.\u00a0 I have a demo with them and able to play around with their tool.\u00a0 LINT is the HDL linting tool.\u00a0 Other than having a filmsy GUI and integrated with Verdi, I don’t see any advantage over HAL.\u00a0\u00a0 IIV is a tool for imply intention verification, which analyze the HDL code and check it against 20 predefined checks.\u00a0 LINT catches syntax error and combination error, IIV obviously sequential error like dead state in a state machine.\u00a0 I don’t think IIV is very useful since the user cannot define custom checks.\u00a0 The built-in checks only catch careless mistakes or stupid logical error made by co-op students.\u00a0 XV is their tool for ‘X’ propagation verification.\u00a0 It is still in beta.\u00a0 The tool reads the RTL code, generate a small Verilog testbench which poke internal signal to ‘X’ and check the propagation.\u00a0 The tool then run that small testbench on your normal simulator and see any ‘X’ is propagated anywhere.\u00a0 I doubt the usefulness of this tool.\u00a0 Lastly, they have ABV for formal assertion checks, but they don’t have a demo setup.\u00a0 I suspect the tool is not ready even a working beta.\u00a0 I am not very impressed by Realintent, if their tools works just advertised, we will probably save a few days of debug time in the beginning and that’s it.\u00a0 I am always skeptic about their claim.<\/p>\n

    Aldec<\/strong>
    \nThey used to provide OEM simulator to Xilinux and other FPGA vendors, now they are selling it as a standalone simulator. The simulator runs on Windows and Linux. It comes with a lint tool and support assertion checking (but not formal analysis). This tool targets FPGA designs, since it probably won’t able to handle 50Mil gates ASIC design. The IDE GUI is simple and pretty, but lacks features and strength of IES. <\/p>\n

    IBM<\/strong>
    \nI went to the IBM booth to find out what’s new in DOORS and vManager integration. The IBM guy brings in Michael Mussey from Cadence, who overseas the vManager project, when he walked by us. In short the integration is not yet working. In the planing front, DOORS will generate the vPlan file from the design spec, verifiers only have to map the coverage and checkers in the vPlan, via a RIF (requirement input format) XML file. In the reporting from, Cadence is working on a script take the vPlan and UCM, generate a UCIF (universal coverage input file) and feed it back to DOORS. Another potential application is use DOOR for verification schedule, DOORS has a plugin that talk to Microsoft Project. It looks like historical data is not saved in DOORS, DOORS only report the current view. Michael from Cadence mentioned that they are adding a MySQL backend to vManger to report historical data. I think we can look into using this new feature to replace our Excel spreadsheet. DOORS has bug tracking tool integration as well. A confirmed bug report should automatically trigger a change request in the requirement spec. We may need to upgrade our the PREP system to work with DOORS.<\/p>\n

    Nextop<\/strong>
    \nThe Nextop is very interesting. It generate assertion (PSL or SVA) automatically from monitoring your simulation. It is an unique solution to address the problem of who writes the assertion. Their tool will analyze how the signals is used in the simulation and generate a list of PSL or SVA statement as the properties of the block. Then the designer have to go through the list (a few hundreds of them) and categorize whether the should always hold true (an assertion) or it’s only true because we haven’t run enough stimulus. (a coverage) Then we the testbench will incorporate the assertions and use them for the rest of the simulation. My only concern is their solution seems too good to be true and I can’t tell the quality of the auto-generated assertion from the demo. I would like to evaluation this tool and is the generate asserted useful or just junks. The simulation over is about 10-15% when the tool is turned on to collect information. Currently, it only work on block level at the moment and the biggest size they had ever tried only has 12K line of code. The designer is weakest link in their flow, since the designer has to check and classify each generated assertion one by one. <\/p>\n

    eVe<\/strong>
    \nThey make emulation box. They talk about testbench speed up, so I am interested in their presentation. But it turns out they mean their box only support synthesable testbench. They don’t have any interface for the FPGA array to communicate with the simulator. They keep telling me that I can easily hook up the emulation box with the simulation by building custom PLI function. Yeah, right. It looks like there are not many emulation box support simulation acceleration out there. Probably it is only supported by the box from the big 3 simulator vendors.<\/p>\n

    ExpertIO<\/strong>
    \nVerification IP vendor. They have Ethernet, SAS, SATA, FC VIP. The offering looks good but the only problem is the VIP is implemented in encrypted behavioral Verilog with SystemVerilog wrapper to control the transactor. They refuse to show me how the API of the VIP looks like unless PMC went through the official NDA process. The only information I can get is the a useless feature list of their VIP but I can’t tell how easy or annoying to use their VIP.<\/p>\n","protected":false},"excerpt":{"rendered":"

    In the 2nd day of DAC, I attended a technology Session Bridging pre-silicon verification and post-silicon validation, a user track presentation on An Open Database for the Open Verification Methodology Synopsys VCS demo and verification luncheon, visited the booth of the following companies: Realintent, Adlec, IBM, Nextop, eVe, ExpertIO Bridging pre-silicon verification and post-silicon validation … Continue reading DAC Technical Review (Day 2)<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"lc_iscn_info":[],"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[1],"tags":[662],"class_list":["post-4515","post","type-post","status-publish","format-standard","hentry","category-_scribble","tag-dac"],"yoast_head":"\nDAC Technical Review (Day 2) - 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I signed up to a full day technical workshop Choosing Advanced Verification Methodology. After the workshop ended at 3:30p, I managed to checked out a few companies in the exhibition floor Vennsa Technologyies, Agnisys Inc and Veritools Advanced Verification Methodology\u2026","rel":"","context":"In "Daily Scribble"","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":4527,"url":"https:\/\/www.horace.org\/blog\/2010\/06\/23\/dac-technical-review-day-45\/","url_meta":{"origin":4515,"position":1},"title":"DAC Technical Review (Day 4,5)","author":"hevangel","date":"June 23, 2010","format":false,"excerpt":"The exhibition floor is over in day 4 and 5. In day 4, I attended user track presentation on verification and a technical session on What input language for HLS. In day 5, I attended a workshop on Software Engineering using Agile Software Development technics User track presentation on verification\u2026","rel":"","context":"In "Daily Scribble"","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":3010,"url":"https:\/\/www.horace.org\/blog\/2009\/05\/29\/10-myths-about-verification\/","url_meta":{"origin":4515,"position":2},"title":"10 Myths About Verification","author":"hevangel","date":"May 29, 2009","format":false,"excerpt":"Every verification engineer should remember this list by heart so that they can educate their managers. The list is so true that I print a copy and pin it to my cube \u201cThis is legacy code no need to verify it\u201d - Hold your horses! are you 100% sure that\u2026","rel":"","context":"In "Know How"","block_context":{"text":"Know How","link":"https:\/\/www.horace.org\/blog\/category\/_reference\/_knowhow\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":4521,"url":"https:\/\/www.horace.org\/blog\/2010\/06\/17\/dac-technical-review-day-3\/","url_meta":{"origin":4515,"position":3},"title":"DAC Technical Review (Day 3)","author":"hevangel","date":"June 17, 2010","format":false,"excerpt":"In the 3rd day of DAC, I went to the user track presentation on formal verification, checked out the booth of Onespin, Jasper, SpringSoft, Tuscany, AMIQ, Starnet, Forte Design System and Cypber WorkBench User track presentation on formal verification The user track presentation is where users of the EDA present\u2026","rel":"","context":"In "Daily Scribble"","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":1653,"url":"https:\/\/www.horace.org\/blog\/2007\/12\/20\/patent-review-meeting\/","url_meta":{"origin":4515,"position":4},"title":"Patent review meeting","author":"hevangel","date":"December 20, 2007","format":false,"excerpt":"Somehow I have to get up early every day this week, today is a 8a.m. patent review meeting.\u00a0 I was asked to sit in the meeting to review two verification related the patent application from Israel.\u00a0 Verification related IP is really hard to patent, it is not that we are\u2026","rel":"","context":"In "Daily Scribble"","block_context":{"text":"Daily Scribble","link":"https:\/\/www.horace.org\/blog\/category\/_scribble\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":3829,"url":"https:\/\/www.horace.org\/blog\/2009\/12\/08\/what-makes-a-great-verification-team-great\/","url_meta":{"origin":4515,"position":5},"title":"What Makes A Great Verification Team Great?","author":"hevangel","date":"December 8, 2009","format":false,"excerpt":"Here is some words of wisdom on verification from thinkverification.com. I could not agree with this article any more, especially on the last point. We verifiers should education the importance of verification to the company, especially to the executives who make the budget decision. Your tool provider won\u2019t tell you\u2026","rel":"","context":"In "News Clips"","block_context":{"text":"News Clips","link":"https:\/\/www.horace.org\/blog\/category\/_reference\/_newsclips\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]}],"jetpack_likes_enabled":false,"amp_enabled":true,"_links":{"self":[{"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/posts\/4515","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/comments?post=4515"}],"version-history":[{"count":5,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/posts\/4515\/revisions"}],"predecessor-version":[{"id":4520,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/posts\/4515\/revisions\/4520"}],"wp:attachment":[{"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/media?parent=4515"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/categories?post=4515"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.horace.org\/blog\/wp-json\/wp\/v2\/tags?post=4515"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}