Tag Archives: verification

Prototypical: The Emergence of FPGA-Based Prototyping for SoC Design – Daniel Nenni & Don Dingee

Prototypical cover front

高科技與歷史,兩樣風馬牛不相及的事情,今次竟然放在同一個句子上。這是一本關於高科技行業歷史的書,作者Dan Neenni是半導體業界的老行尊,他建立的semiwiki.com網站,是矽谷業界重要的資訊來源。這本書是去年我去Design Automation Conference(DAC)免費拿回來,還有作者親筆簽名。剛好今個project要做FPGA prototyping,這本書正好有用,短短一百頁,半晚便看完。

FPGA Prototyping是什麼?在半導體中,最為人熟識是CPU,即是電腦的運算核心,汎用處理器,只要寫軟件,什麼程式也可以執行。不過由於CPU行軟體,不論在速度和耗電,遠遠不及把程式寫在硬體的ASIC。不過ASIC有一個大問題,就是程式寫了入硬體就不能更改。軟體出錯要修正行簡單,下載新的軟體版本就行了,但ASIC有錯要修正就要重製,還未計算要回收市面上有問題晶片的成本。大慨就如古代要刻石板寫字,寫錯一個字要成塊石板重寫一般麻煩。FPGA是集CPU和ASIC兩家之長,執行速度比媲ASIC,程式相對容易地修正,不過價錢卻十分昂貴。一般而言,如果產品講求靈活彈性,用CPU。如果產品的件數夠多,重視執行速度和耗電,而程式可以寫死不用更改,就用ASIC,兩頭唔到岸的就用FPGA。

設計ASIC由於不能出錯,投產前的測試十分重要,一般用CPU軟體去模擬程式,缺點是運行速度非常慢,FPGA的運行速度和可以重寫的特性,正好適合用來測試ASIC。當然不是買一顆FPGA回來自已砌,FPGA prototyping已是一個完整的eco-system,發展出不同的設計工具和流程,讓工程師很輕鬆的把ASIC放入FPGA上測試。詳細的內容十分技術性,說了也沒有人看得明白,從略。


IP Integration : What is the difference between stitching and weaving?

I should write a article on: What is the difference between reusing and salvaging…

by David Murray, 12/15/2010, Design and Reuse

As a hardware design engineer, I was never comfortable when someone talked about IP integration as ‘stitching a chip together’. First of all, it sounded like a painful process involving sharp needles, usually preceded by a painful accident. I happened to be the recipient of said stitches when, at 8 years of age, I contested a stairs post with my forehead, and sorely lost. I have to say, luckily, I have been quite adept at avoiding the needle and thread ever since. That was of course until once when, an hour before that important customer presentation, my top-shirt button, due to an over enthusiastic yawn, pinged across my hotel room floor like a nano-UFO. A panicked retrieval of the renegade button was followed quickly with a successful hunt for an elusive emergency sewing-kit. The crisis quickly dissipated as I stitched back the button in a random-but-directed type of methodology. Needle-less to say stitching, whilst sometimes necessary, makes me uncomfortable.

Stitching, according to Wikipedia, is “.. the fastening of cloth, leather, furs, bark, or other flexible materials, using needle and thread. Its use is nearly universal among human populations and dates back to Paleolithic times (30,000 BCE).” It also states that stitching predates the weaving of cloth. So, 32,000 years later, in these hi-tech times we are still stitching things together. It’s not fur this time, but ‘ports’. Stitching a chip together involves connecting ports together with wires. (Note the terminology also where, if you don’t use certain ports you ’tie’ them off).

Weaving is a different game altogether. One definition simplifies weaving as ‘creating fabric’. Thus a key differentiator between stitching and weaving is that stitching may refer to fixing/mending things whilst weaving is used to create. Stitching is an emergency, an ah-hoc approach (please refer to my stitched button above) whilst weaving is more structured, more planned. Stitching invokes the image of being bent over, eyes squinted, immersed in the tiniest of detail. Weaving is more graceful and productive. In IC design flow terms, I equate stitching with scripting. It is task that is useful to join pieces of the flow together. Weaving creates something. It transforms thread to cloth, and therefore equates more to synthesis. Weaving is a process.

So when it came to developing and naming a tool used to effectively integrate IP and create a chip hierarchy, in a structured manner, we didn’t consider consider ‘STITCHER’ – It had to be ‘WEAVER’.

Stitching is important to fix things, and is necessary in emergency situations, however it has its limitations and as if used as a core creation process, it may come undone. So as I ranted on during that vital presentation, as I got to the cusp of the value-add, I curbed my enthusiasm, keep it slightly in check just in case those button stitches came undone and resulted in a serious eye injury of an altogether innocent customer. What then, of those poor stitched chips? What if those threads start to unravel and your chip integration is running very late. You may have to resort to different type of Weaving, when dealing with your management, customers or partners.

What Makes A Great Verification Team Great?

Here is some words of wisdom on verification from thinkverification.com. I could not agree with this article any more, especially on the last point. We verifiers should education the importance of verification to the company, especially to the executives who make the budget decision.

Continue reading What Makes A Great Verification Team Great?

Cadence and my friend’s love story

I had to come to work early today to meet up with the representative from Cadence. Somehow I am chose to baby sit them, give them the requirement from the team. I have a feeling they come to help us just because they want to have Cadence’s product more erode into PMC’s tool chain. So I end up not thing any work at all today. Make it worse, I have to come in early tomorrow morning to let them into the building as well. One good thing about it is one of the representative is base off in Toronto. I am looking forward to keep him as a contact in what company that I may potentially switch when moving back home. Companies using Specman would make a perfect match for my skill set.

The story of my friend and her new crush keeps evolving and it’s getting more and more interesting. It seems she already know more about that guy than I do, even though it is me who introduce her the guy. Let’s see how this romantic adventure will turns out, Pat and I will pay close attention to the latest development.